1. Field of the Invention
The present invention relates to an algorithmic pattern generator.
2. Description of Related Art
Integrated circuit (IC) tests are typically organized into a succession of test cycles. An IC test is normally defined by a separate sequence of data values (vectors) for each pin of an IC device under test (DUT), with each vector indicating the test activities to be carried out at a DUT pin during a test cycle. A typical integrated circuit (IC) tester includes a separate tester channel for each DUT pin. Each tester channel includes a pin testing circuit for carrying out the test activities indicated by the channel's vector sequence and a memory for storing and reading out vectors to the pin testing circuit. A central pattern generator provide an address to each vector memory in response to each pulse of a clock signal, and the vector memory of each channel reads out an addressed vector to the channel's pin testing circuit. Integrated circuit testers with distributed pattern generators don't use a central pattern generator; they employ a separate pattern generator in each tester channel for directly generating vectors.
Many types of pattern generators are known. A simple pattern generator includes a random access memory storing a data value at each address and a counter for incrementing the memory's address in response to each pulse of a clock signal, thereby causing the memory to read out a data sequence from successive addresses. Such pattern generators have been employed in integrated circuit testers, but as ICs have grown in size and complexity, so too have the size of the vector sequences needed to define IC tests. This has required an increase in the size of the pattern generator and vector memories. Also as the operating frequency of ICs have continued to increase, the test cycle period has decreased. Since a pattern generator must supply a data output at the start of each test cycle, the higher test frequencies require faster vector memories. But large and fast memories are expensive.
Algorithmic Pattern Generators
Since many tests require repeating patterns of vectors, prior art integrated circuit testers have employed algorithmic pattern generators to reduce the amount of data that must be stored. U.S. Pat. No. 4,862,067 issued Aug. 29, 1989 to Brune et al discloses an IC tester employing an algorithmic pattern generator including a vector memory and a memory controller. The vector memory stores both a vector and an instruction at each address. The memory controller addresses the memory before the start of each test cycle and forwards the vector read out of the vector memory to the pin testing circuits. The instruction read out of the vector memory tells the memory controller how to choose the next vector memory address. This vector memory architecture allows instructions telling the memory controller to repeat vector sequences using loops and calls. The memory controller may also be instructed to perform a conditional branch when a signal from the pin testing circuits indicates the DUT output signal meets some criteria. While Brune's system reduces the size of vector memory needed, it requires a fast vector memory having an access time no longer than the period of a test cycle. It also requires that the instruction processor be able to execute an instruction in one test cycle. Thus either the memory access speed or the instruction processing time may limit the frequency at which Brune's system can operate.
Cache Memories
A large dynamic random access memory (DRAM) is inexpensive but it's too slow to be accessed during each test cycle of a high-speed IC test. Some integrated circuit testers reduce memory costs by using a large DRAM to supply data to a small, high-speed cache memory. In such a system, vectors (or vector memory addresses) for N successive test cycles are stored at each memory location of a DRAM. The vector output of the DRAM is written into a high-speed cache memory at a rate that is 1/Nth of the test frequency. The high-speed cache memory then reads out vectors (or vector memory addresses), one at a time, at the required test frequency rate.
It would be desirable to provide a pattern generator for an integrated circuit tester that generates its output vector or address pattern algorithmically and which also uses caching to allow use of lower speed main memories. U.S. Pat. No. 4,931,723 issued Jun. 5, 1990 to Jeffery et al employs a relatively low-speed vector memory storing eight 10-bit vectors as one 80-bit word at each vector memory address. Each 80-bit word read out of the vector memory is shifted into an 80-bit shift register. The shift register which, acting like a small cache memory, shifts out a 10-bit vector to a pin testing circuit at the start of each test cycle.
Jeffery's system is capable of limited algorithmic vector generation in that it can repeat sequences of instructions. Only the first instance of a repeating vector pattern is stored in the vector memory. Upon encountering that first instance of that pattern during the test, a vector memory controller, in addition to sending the pattern to the pin testing circuits, also saves that instance of the vector pattern in (another) cache memory. Thereafter, when the controller reaches the end of a loop, it starts reading the vectors out of the cache memory instead of the vector memory, and can do so as many times as the pattern "loop" is to be repeated.
In order to repeat a sequence of instructions, the memory controller has to know the starting and ending vector memory addresses of the loop as well as the number of times the loop is to be repeated. In Jeffery's system, loop start and loop end instructions are inserted into the vector sequence. Thus at the start of a test signal in which a loop begins or ends, the vector memory reads out an instruction instead of a vector. Since a vector has to be provided to the pin testing circuit at the start of every test cycle, the appearance of a loop instruction causes a gap in the vector sequence. Jeffery uses the cache memory to solve this problem.
Before the start of a test, the vector memory controller receives an instruction indicating the positions in the vector sequence output of the vector memory of starting and ending vectors of the first loop as well as the number of repetitions to be performed. During the test, when the vector memory controller encounters the first vector of the first loop, it begins storing vectors of the loop in the cache memory until it reaches the last vector of the loop. At that point it begins reading the vectors out of the cache memory instead of reading them out of the vector memory. An instruction indicating the starting and ending addresses and length of the second loop is stored in the vector memory immediately following the last vector of the first loop. During the second pass though the first loop, while the memory controller is reading vectors out of the cache memory, the memory controller also reads the instruction for the second loop out of the vector memory. Thus the cache memory provides the memory controller with an alternate source of vectors during the time that it is reading a next loop instruction out of the vector memory. This eliminates the gap in the vector sequence caused by the inserted loop instruction. While Jeffery's system takes advantage of both memory caching and algorithmic pattern generation, its algorithmic pattern generation capability is rather limited. Jeffery's system can only perform loops; it cannot perform subroutine calls or conditional branches.
Pipeline Instruction Processors
Some pattern generators include an instruction processor and a memory with instruction and pattern data concurrently stored at each memory address. When an instruction/pattern data pair is read out of the memory, the pattern data provides the pattern generator output. The instruction tells an instruction processor how to select the memory address of the next instruction/pattern data pair to be read out. Such pattern generators can employ a wide variety of instructions including calls, returns, branches, loops etc. However since an instruction processor must decode the instruction at the start of a test cycle and be ready to jump to a new memory address by the start of the next test cycle, the speed at which the memory controller can decode instructions can limit the pattern generator's operating frequency.
In some applications, high-speed instruction processors employ a pipeline architecture to decode and execute instructions. In a pipeline processor instructions are sequentially clocked through many processing stages, with successive instructions being concurrently processed by successive pipeline stages. Since the amount of processing each stage requires to process an instruction is relatively short, the clock signal clocking the instructions through the stages may be of relatively high frequency. Although the total time required for all pipeline stages to fully process an instruction may be relatively long, the instruction processor can complete processing an instruction on each pulse of the clock signal. Thus the pipeline processor processes instructions at the high clock frequency.
Although they can processes instructions at high frequency, pipeline instruction processors have not been used in pattern generators. Assume, for example, that a pipeline instruction processor normally reads vectors sequentially out of a vector memory at the start of each test cycle, but may jump to some other memory address in response to an instruction such as a branch, call or return requiring an address jump. Suppose also that a pipelined instruction processor requires N clock cycles to fully process an instruction. When the instruction processor encounters an instruction requiring an address jump, we want the processor to make the jump immediately in the next test cycle in order to maintain the continuity of the pattern generator output. But since it actually requires N test cycles to make the jump, the processor will continue to read instructions stored in the next N memory addresses. That extra set of N instructions causes a sequence of N pattern data values to be inserted into the pattern generator's output data sequence.
What is needed is an algorithmic pattern generator employing a cache memory system and which uses a pipeline instruction processing architecture without inserting extra data into its output data pattern prior to each memory address jump.